Field of Invention
This invention relates to an integrated circuit (IC) process, and particularly relates to a process for fabricating a three-dimensional (3D) memory, and to a structure of a 3D memory of which the fabrication includes the same process.
Description of Related Art
As the demand for storage subsystems of electronic products is increased, the standard for the read/write speeds or capacities of products is higher, so high-capacity related products have become the mainstream in the industry. Therefore, 3D memory, especially 3D vertical-gate (VG) NAND flash memory, has been developed recently.
In a conventional vertical-gate 3D memory process, a plurality of linear stacks each including alternately stacked gate lines and insulating layers are formed, a thin amorphous silicon layer is formed and then annealed to form a thin polysilicon channel layer, and then contact plugs are formed on the channel layer above the linear stacks.
However, because agglomeration easily occurs on the silicon layer in the annealing, portions of the channel layer on opposite sidewalls of the linear stacks may be connected by the agglomeration to cause short circuits, especially when the process linewidth is small.
Moreover, since the polysilicon channel layer is thin, the contact plugs are difficult to land on the channel layer above the linear stacks.